1. Field of the Invention
The present invention relates to an MOS (Metal Oxide Semiconductor) dynamic RAM (Random Access Memory) comprising a plurality of trench memory cells.
2. Description of the Prior Art
A random access memory (RAM) comprises a memory cell array having a plurality of memory cells arranged in a matrix and selecting means for selecting a single memory cell from the memory cell array, information being written into a memory cell selected by the selecting means or information stored in the memory cell selected by the selecting means being read out.
FIG. 1 is a diagram showing an example of an equivalent circuit of a dynamic type memory cell.
In FIG. 1, charges are stored in a capacitor 13 from a bit line 11 through an MOS transistor 12, and information is stored depending on the presence or absence of the charges. When a predetermined potential is applied to a word line 14, the MOS transistor 12 is rendered conductive. As a result, information can be written or read out. Each of the above described memory cells comprises an MOS transistor and a charge storage region (capacitor) formed on a semiconductor substrate. Recently, a trench memory cell in which a trench is formed on a semiconductor substrate and a charge storage region is formed in the inner surface of the trench has been developed for high integration of a semiconductor memory device.
FIG. 2A is a plan view showing an MOS Dynamic RAM comprising conventional trench memory cells (trench type memory cells) arranged for a folded bit line system, and FIG. 2B is a cross sectional view taken along a line II--II shown in FIG. 2A.
The trench memory cells are proposed in, for example, Lecture Number 9.6 in International Electron Device Meeting in 1984 (IEDM'84).
In FIGS. 2A and 2B, a pluraliy of memory cells 2 are formed in the surface of a p type semiconductor substrate 1, and isolating oxide films 3 are formed between the memory cells 2. Each of the memory cells 2 comprises a charge storage region 4 for storing charges, a transfer gate region 5, and an n type impurity diffusion region 6 connected to a bit line 7. The above described charge storage region 4 is provided in a trench 8 (a region enclosed by a thick solid line in FIG. 2A) formed in the surface of the semiconductor substrate 1, and comprises an n.sup.+ layer 41, an insulating film 42 for a capacitor, and a cell plate 43. The n.sup.+ layer 41 is formed in the bottom surface portion and the side surface portion of the trench 8 for a cell, and the cell plate 43 comprising polysilicon is formed in the upper portion of the n.sup.+ layer 41 through the insulating film 42 for a capacitor. As a result, charges are stored in the n.sup.+ layer 41. The transfer gate region 5 comprises a channel region 51 between the impurity diffusion layer 6 and the n.sup.+ layer 41 in the trench 8 for a cell, and a word line 9 comprising polysilicon formed in the channel region 51. The impurity diffusion region 6, the transfer gate region 5, and the n.sup.+ layer 41 in the charge storage region 4 constitute a switching transistor. When a predetermined potential is applied to the word line 9, an inversion layer is formed in the channel region 51, and information stored in the bit line 7 is transferred to the charge storage region 4 through the channel region 51.
Therefore, when charge storage capacitance (capacitance between the n.sup.+ layer 41 and the cell plate 43) is provided in the trench 8, large charge storage capacitance can be obtained with the reduced area, and integration is increased. In addition, an MOS dynamic RAM having large capacitance which is immune to soft errors such as alpha-particles, the other noise or the like can be achieved.
In the MOS dynamic RAM comprising the above described conventional trench memory cells, the p type semiconductor substrate 1 is generally set to a negative potential (about -3 V), and a potential of about 5 V or about 0 V corresponding to information "1" or "0" is applied to the n.sup.+ layer 41 serving as a charge storage node.
FIG. 3 is an enlarged cross sectional view showing trenches in the adjacent two memory cells shown in FIG. 2B.
In FIG. 3, when for example, the potential of an n.sup.+ layer 41a in a trench 8a in one memory cell 2a becomes 0 V and the potential of an n.sup.+ layer 41b in a trench 8b in the other memory cell 2b becomes 5 V, depletion regions 10a and 10b are formed on the side of the semiconductor substrate 1 on the n.sup.+ layer 41a and the n.sup.+ layer 41b.
Thus, if the adjacent trenches 8a and 8b are formed to be closer to each other, the above described depletion region 10a and 10b contact with each other, so that punch-through occurs between the memory cells 2a and 2b.
Therefore, intervals a and b (see FIG. 2A) between adjacent trenches 8a and 8b can not be decreased, which presents a large problem in providing high integration.
To avoid this, some methods are proposed. For example, trench memory cells may be formed in a p well having a high concentration so that expansion of the depletion region 10a and 10b is controlled. Alternatively, an epitaxial substrate may be used. However, the well having a high concentration reduces the breakdown voltage of memory cells and a semiconductor substrate. Furthermore, the epitaxial substrate is expensive.